In on-chip and inter-chip data communication systems where high data bandwidth is required, power dissipation and chip area of input/output (I/O) circuits are crucial design factors to be considered. For instance, modern multi-core microprocessors have thousands of bits of on-chip data buses connecting processor cores and caches. In high-performance servers, the inter-chip links from processors to network switches or off-chip caches also require I/O buses hundreds of bits wide running at multiple Gb/s per lane data rates. Compact and low-power I/O schemes are needed for these high-performance systems.